The present invention generally relates to semiconductor processing, and more particularly to a method of fabricating isolation regions, such as shallow trench isolation (STI), in which the stress of the isolation region has by modulated by a nitrogen plasma treatment. The isolation regions created in the present invention, which are particularly useful in small width devices (on the order of about 0.25 Âμm or less), have substantially little or no bird beaks in the isolation region.
In the semiconductor industry, it is well known to isolate one or more device regions present on a semiconductor structure using isolation regions such as shallow trench isolaton (STI) regions. A standard STI process is shown, for example, in FIGS. 1A-1C. Specifically, prior art FIG. 1A illustrates an initial processing step in which a pad stack comprising an oxide 12 and a nitride 14 is formed atop a surface of a semiconductor substrate 10. An optional hard mask (not shown) may also be formed atop the nitride layer 14 of the pad stack.
Next, lithography is employed in providing a trench pattern to the structure. Specifically, the trench pattern is formed by first applying a photoresist on the upper surface of the pad stack. The photoresist is then exposed to a pattern of radiation and thereafter the pattern in the photoresist is developed using a resist developer. An etching step is used to transfer the pattern from the photoresist into the nitride layer 14. After the initial pattern transfer, the photoresist is removed utilizing a stripping process and then etching continues through the oxide layer 12 stopping atop an upper surface of the semiconductor substrate 10 so as to provide a structure having an opening 16 in the oxide layer 12 as shown, for example, in FIG. 1B.
After providing the structure shown in FIG. 1B, a trench is formed in the semiconductor substrate 10 via etching through the opening 16. A trench liner (not shown) is typically formed via oxidation on the bare sidewalls of the trench including the sidewalls of the oxide layer 12. The trench is then filled with a trench dielectric material 22 such as SiO2, tetraethylorthosilicate (TEOS) or a high-density plasma oxide and thereafter the structure is planarized to the upper surface of the nitride layer 14. A deglazing process may follow the trench fill step. After deglazing, the nitride layer 14 is removed providing a structure having an STI region 24 formed in the surface of the semiconductor substrate 10. The structure including STI region 24 is shown, for example, in FIG. 1C.
The oxide layer 12 may be removed prior to CMOS (complementary metal oxide semiconductor) device fabrication. CMOS device fabrication may include the following processing steps:    1. A conventional gate oxidation pre-clean, and gate dielectric formation;    2. Gate electrode formation and patterning;    3. Gate reoxidation;    4. Sourceldrain extension formation;    5. Sidewall spacer formation by deposition and etching;    6. Source/drain formation;    7. Silicide formation; and    8. Back-end-of-the-line (BEOL) process.
During the oxidation procedures used in steps 1 and 3, bird beaks 26 begin to form in the STI regions 24 at or near the interface between the STI 24 and the semiconductor substrate 10; bird beaks are oxide regions that are formed during CMOS device oxidation processes that encroach upon and, in some instances, enter the islands of the semiconductor substrate 10 which lie adjacent to the STI regions. This encroachment and subsequent entry into the semiconductor islands causes the semiconductor substrate 10 to exhibit uneven stress in the active device areas. This uneven stress may negatively impact some of the devices, while positively affecting other devices present on the semiconductor substrate. Bird beak formation is particularly relevant for small width semiconductor devices that have a width of about 0.25 Âμm or less.
Specifically, stress caused by bird beak formation is known to lead to device degradation for NFET devices and device improvements for PFETs. In particular, the device drive current and the device on-current can be affected (either negatively or positively) by bird beak formation. To date, applicants are unaware of any prior art method that seeks a means to tailor the stress caused by bird beak formation so as to improve the device performance of NFETs and PFETs.
In view of the drawbacks mentioned above with the prior art process of fabricating STI regions, there is a need for providing a method of forming isolation regions such as STIs, in which bird beak formation is substantially prevented thereby reducing the stress in the semiconductor substrate. There is also a need for providing a method in which stress formation is controlled such that improved device performance, in terms of drive current and on-current, can be achieved for a structure containing both NFETs and PFETs.